Introduction
The constant evolution of technology has significantly impacted the computer system storage innovations to achieve efficiency with improved performance and reduced data processing time. New technology has resulted in the invention of solid-state drives that uses semiconductor chips to store data in a non-volatile mode using flash memory.
History of Solid-Sate Drives
The technology concept in solid-state drive (SSD) memory dates back to the 1950s where IBM developed the first non-volatile solid-state memory technology, which they called Card Capacitor Read-Only-Store (CCROS) (Garner & Dill, 2010). Later around the same time, IBM developed another SSD technology needed magnetic core memory and was based on the electromagnetism concept (Waaben, 1966).
The use of the semiconductor memory method in the SSD was first implemented in the 1970s and 1980s in Cray, Amdahl, and IBM supercomputers. The innovation was not used widely due to the high prices to acquire the SSD storage drives. The use of electrically alterable read-only memory was produced by the General Instruments in the late 1970s and had a similar operation as the NAND Flash memory that was invented later (Micheloni, 2017).
In 1978, a company called Texas Memory Systems produced solid-state RAM that was 16 kilobytes to be used in the acquisitions of seismic data by oil companies. The first RAM solid-state drive was introduced in 1979 by Storage Trek company.
Flash-based SSD was first announced in early 1995, which supported non-volatile memory and did not require batteries to hold data in the memory (Garner & Dill, 2010). The SSD was resistant to malfunctions as they could withstand extreme shocks, high temperatures, and vibrations. The PCIe-based SSD was introduced in 2007 and was capable of handling 100000 operations, both input and output per second, and had storage capabilities of supporting up to 320GB (Micheloni, 2017).
Need for flash-based memory innovation
The access time for the SSD is high, with speeds ranging from 35 to 100 microseconds providing performance efficiency faster than the traditional hard drives. Program execution and data processing are made faster, resulting in time efficiency. The flash memory SSD technology is more reliable compared to the traditional hard drive, which uses a rotating platter to store and access data. The SSD uses flash memory, which does not involve any movement, which increases its lifetime with reduced tear and wear. The traditional hard drives are prone to malfunction resulting from the platter rotations leading to data loss. The power consumption of SSD innovation is efficient compared to hard drives since it uses NAND flash memory with electric cells that store electric charge, which is used in cell programming even in power outages (Sang Lyul Min, 2010).
SSD V-NAND memory chip
The V-NAND innovation was first produced by Samsung Group to replace the traditional planar NAND (Xiao, 2018). The flash memory uses a V-NAND logic gate chip and consists of an array of transistors that have floating gates each. The floating gates trap every charge that regulates the switching on the transistors preventing biased charge affecting data volatility (Xiao, 2018). The V-NAND technology offers storage size expansion advantages over the traditional planar NAND, which facilitates the stacking of cell layers on one another.
Fig. 1.1 V-NAND stacking logic structure
This Samsung V-NAND technology enhances increased performance and greater SSD densities without increasing the SSD size (Xiao, 2018). The V-NAND innovation in SSD includes integration of advanced flash controller, which consumes half the power required in traditional planar NAND to process instructions when handling data. The coupled layering technology has resulted in expansion flexibility enabling packaging of 1TB (Terra Bytes) SSD in early 2017. Heavy applications resources and data can be processed within reduced processing time and with greater efficiency. The stacking of cell layers has enhanced effective trapping of charge, which increases the density but maintains the size of the SSD without impacts of cell-to-cell interferences (Micheloni, 2017). The transistors act like bits of a non-volatile memory enabling data storage even when there are sudden power outages (Xiao, 2018).
Samsung Evo M.2 ssd 1tb Parts
Part 1 Flash Memory
The flash memory array is segregated independent blocks that form the smallest erasable storage unit. The execution of an erase execution three actions are prompted: the content address location verification, application of program pulse on all the sector cells where the data being erased was stored, and erasing of all cells within the sector specified by the address location (Xiao, 2018). The V-NAND flash technology supports Multilevel Cell technology (MLC), which enables storage of 3 bits in a single cell, unlike the single-level cell (SLC) that supports only a single bit per cell. The erasing process in the MLC SSD is more efficient and faster compared to the use of the SLC concept (Fazio, 2006). The deployment of the MLC in the V-NAND technology has increased the SSD performance and durability resulting from the increased utilization of cell capacity (Arafat et al., 2018).
Each storage block on each transistor consists of a set of addressable pages with the MLC architecture holding 128 pages per block. Each of the pages on the block storage units consists of additional supplementary bytes that hold the Error Collecting Code (ECC) information and other metadata required implementing the storage approach. The NAND approach considers a page as the smallest unit that can be programmed (Arafat et al., 2018). The programming process of a page involves sequential writing of volatile registers into a page. The data in the page is then converted into a non-volatile flash page through write commands sent to the chip (Sang Lyul Min, 2010).
Each of the pages on the flash memory can assume one of the three distinct states: valid, invalid, and erased/free state. In situations where the pages do not have any data written into them, the pages are in an erased/free state. The pages in the erased state are the only pages that can allow a write instruction to be performed in which case they change their status to a valid state. The erase instructions can be applied to pages invalid state to delete the data contents and change their state to free or erased. The invalid pages in the flash memory are managed by the flash translation layer FTL, which consists of a garbage collector algorithm to collect invalid state pages and convert them to free or erased pages ready for writing (Sang Lyul Min, 2010).
Fig. 1.2 Flash memory structure
Part 2 The Multiplexer Modern flash memory supports multichannel, where single flash memory is integrated with multiple controllers ensuring parallelism with improving levels of latency (Suzuki et al., 2018). The FTL directly receives the request from hosts and converts the physical addresses into logical addresses and prompts the multiplexer crossbar switch to access the flash memory (Sang Lyul Min, 2010). The Multiplexer selects the appropriate controller to be used to access the flash memory (Liu et al., 2012). The controller converts the logic address to main logic and control logic, which contains the main data and control signals, respectively.
Fig. 1.3 Logic structure of Multiplexer
Part 3. System Unit
The FTL consists of the wear leveler algorithm that manages the use of storage blocks within the flash memory through even writing distribution to avoid biased wear of some storage blocks compared to others (Suzuki et al., 2018). The wear-leveling process ensures prolonged SSD lifetime by ensuring dynamic wear leveling in the repositioning of storage blocks.
Relevant instructions are decoded when the correct sequence of commands is received, resulting in the generation of control signals from the command interface, which allows the memory to begin the execution of the decoded instruction. When a program or erase instructions get decoded, input buffers corresponding with the related address are fetched and processed by the relevant instruction controller (Suzuki et al., 2018).
A program instruction automates two actions: conduct verification of the address locations of the required data and application of program signals on non-programmed cells. The program verification action uses engages normal read circuits to loop through address locations to detect matching addresses in the memory array and with the help of sensors to detect affirmation to read the content of the obtained cells (Liu et al., 2012)
The NAND scaling facing the semiconductor technology is addressed by Samsung Group V-NAND innovation by allowing a V-shaped stacking in a vertical layering. The mapping length for SSD cells reduced from 20nm to 3Xnm in the V-NAND technology solving the challenges that previously impacted the traditional planar NAND (Fazio, 2006). The Charge Trap Flash (CTF) in V-NAND innovation has solved the interference problem between cells resulting in no static charge being stored temporarily on non-conductive surfaces. The V-NAND innovation modifies the CTF design by coating the logic gates and cell channels with an insulator, which prevents charge from dissipating to neighboring components (Takeuchi, 2010). The power consumption by the CTF to program cells is minimized, resulting in reduced voltage requirements to program a single cell (Suzuki et al., 2018). With reduced voltage, the NAND cells are impacted with reduced stress improving durability, endurance capabilities, and its lifetime in general.
Part 4 SSD controller
The SSD controller is assaulted with a DDR4 memory pool, which enables the control and management of the V-NAND. The controller is integrated with the flash memory using channels of memory parallel to each other. The controller communicates the host requests to the FTL, which controls the write, read, and erase instructions with the help of the wear leveler and garbage collection algorithms. The FTL wear leveler algorithm controls the cell distribution to ensure uniform cell tear and wear. The garbage collection algorithm controls the erasing process of cells in invalid states (Arafat et al., 2018).
Part 5 SSD Interface and usability
The Samsung Evo SSD technology uses M.2 innovation without SATA ports enabling them to slid directly into device slots. The M.2 innovation supports compatibility and is more flexible and compared to traditional SATA based drives. The M.2 interface supports Non-volatile Memory Express (NVMe), which allows for effective data transfer speeds of uptown 4GB/s, unlike the trading SATA drives, which are limited to low bandwidth data transfer rates. The M.2 interface design experience lower latency rates in data transfer compared to SATA based interface, which is significantly impacted by higher latency rates during data processing between host and the drive (Suzuki et al., 2018).
The Samsung Evo m.2 SSD is used in computer systems for the storage of data and supports writing and reading of information based on V-NAND technology. The SSD has an M.2 interface that connects to compatible devices and computers using a standard IDE. The SSD card is capable of storing information into flash memory cells even in power supply outages using the CTF stored charge. Data stored in the flash memory is accessible using read instruction, which uses address locations to loop through flash memory cells to retrieve requested data (Liu et al., 2012). The write command is passed from the host across the M.2 interface and handled by the controller, which enables sequential volatile data to stream into block pages and then converting them into non-volatile data flash pages. The flash cells are multichannel and support storage of 3 bits in a single cell. The flash memory cells are tapered into stacks where data is stored in stacks of layers.
Conclusion
The Samsung M.2 SSD card uses the V-NAND technology, which enables stacking if cells into layers, which increases SSD density without altering the size resulting in endurance with improved efficiency. The V-NAND innovation was developed by Samsung Group and launched in early 2017 with its main aim being to allow for flexible storage expansion using the cell stacking approach. The V-NAND uses CTF to solve the challenge of cell-to-cell charge interference by wrapping floating gates with a silicon insulator, thereby trapping charge from transferring to neighbored non-conductor components. V-NAND technology has more endurance and power consumption compared to traditional planar NAND innovation.
The V-NAND SSD technology uses the stacking concept to trap charge, which results in reduced voltage requirement to program individual cells. In comparison with the traditional planar NAND technology, power consumption due to cell programming is more efficient in V-NAND innovation (Takeuchi, 2010). The ability to pack more data per die gives the V-NAND approach more scaling efficiency resulting in increased density of SSD with more storage capabilities. The latency levels during data transfer in the V-NAND approach are lower and allow up to speeds of 4GB per second, unlike the traditional planar NAND technology, which experiences high latency and slower speeds of up to 550 Mbs per second (Suzuki et al., 2018). The use of M.2 based interface in the V-NAND SSD supports more usage compatibility resulting in a reliable design which not limited to device interface as it is the case with the earlier SSD SATA interface. In conclusion, the V-NAND technology in SSD is efficient in data storage and has more endurance compared to earlier predecessor innovations like the planar NAND approach. The power consumption in V-NAND in programming flash memory cells is economically efficient and reliable in saving energy.
References
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